EE8351- DIGITAL LOGIC CIRCUITS Syllabus 2017 Regulation

0
253

EE8351- DIGITAL LOGIC CIRCUITS Syllabus 2017 Regulation

EE8351- DIGITAL LOGIC CIRCUITS Syllabus 2017 Regulation

EE8351                                        DIGITAL LOGIC CIRCUITS                             L T P C
                                                                                                                            2 2 0 3

OBJECTIVES:

  • To study various number systems and simplify the logical expressions using Boolean
    functions
  • To study combinational circuits
  • To design various synchronous and asynchronous circuits.
  • To introduce asynchronous sequential circuits and PLDs
  • To introduce digital simulation for development of application oriented logic circuits.

UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES                                                                      6+6

Review of number systems, binary codes, error detection and correction codes (Parity and
Hamming code) – Digital Logic Families -comparison of RTL, DTL, TTL, ECL and MOS
families -operation, characteristics of digital logic family.

UNIT II COMBINATIONAL CIRCUITS
                                                                                      6+6

Combinational logic – representation of logic functions-SOP and POS forms, K-map
representations – minimization using K maps – simplification and implementation of
combinational logic – multiplexers and de multiplexers – code converters, adders,
subtractors, Encoders and Decoders.

UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS                                                                                              6+6

Sequential logic- SR, JK, D and T flip flops – level triggering and edge triggering – counters –
asynchronous and synchronous type – Modulo counters – Shift registers – design of
synchronous sequential circuits – Moore and Melay models- Counters, state diagram; state
reduction; state assignment.

UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABILITY LOGIC DEVICES            6+6

Asynchronous sequential logic circuits-Transition tability, flow tability-race conditions,
hazards &errors in digital circuits; analysis of asynchronous sequential logic circuitsintroduction
to Programmability Logic Devices: PROM – PLA –PAL, CPLD-FPGA.

UNIT V VHDL                                                                6+6

RTL Design – combinational logic – Sequential circuit – Operators – Introduction to
Packages – Subprograms – Test bench. (Simulation /Tutorial Examples: adders, counters,
flip flops, Multiplexers & De multiplexers).

                                                        TOTAL : 60 PERIODS

OUTCOMES:

  • Ability to design combinational and sequential Circuits.
  • Ability to simulate using software package.
  • Ability to study various number systems and simplify the logical expressions using
    Boolean functions
  • Ability to design various synchronous and asynchronous circuits.
  • Ability to introduce asynchronous sequential circuits and PLDs
  • Ability to introduce digital simulation for development of application oriented logic
    circuits.

TEXT BOOKS:

1. James W. Bignel, Digital Electronics, Cengage learning, 5th Edition, 2007.
2. M. Morris Mano, ‘Digital Design with an introduction to the VHDL’, Pearson
Education, 2013.
3. Comer “Digital Logic & State Machine Design, Oxford, 2012.

REFERENCES

1. Mandal, “Digital Electronics Principles & Application, McGraw Hill Edu, 2013.
2. William Keitz, Digital Electronics-A Practical Approach with VHDL, Pearson, 2013.
3. Thomas L.Floyd, ‘Digital Fundamentals’, 11th edition, Pearson Education, 2015.
4. Charles H.Roth, Jr, Lizy Lizy Kurian John, ‘Digital System Design using VHDL, Cengage,
2013.
5. D.P.Kothari,J.S.Dhillon, ‘Digital circuits and Design’,Pearson Education, 2016.

LEAVE A REPLY

Please enter your comment!
Please enter your name here